奎芯科技亮相IP-SoC China 2026 分享高速接口 IP 与 Chiplet 进展

This article outlines the latest industry consensus on the AI chip sector, alongside concrete commercialization progress from Chinese domestic firm Quarkchip in high-speed interconnect and Chiplet technology, serving as a practical, accessible update on cutting-edge developments in the semiconductor space.

1. Core industry trend assessment: The development of large language models has shifted from a phase of raw computing power competition to one focused on interconnect performance. Traditional interfaces can no longer meet the interconnect demands of the Chiplet era, as the primary bottleneck for AI chips moves from the compute capacity of individual dies to the data delivery capability of entire systems. Current interconnect requirements fall into two categories: in-package and die-to-die interconnects to boost single-node performance, and cross-system interconnects to scale node counts. Low latency and low power consumption directly determine both user experience and cost for AI applications.

2. Commercialization progress: Quarkchip’s domestically developed UCIe interface IP has passed rigorous testing with stable performance and strong power efficiency, with its solutions already shipping in volume for enterprise SSD controller applications. The company has also launched an IO Die and customized 3D storage solutions designed to ease HBM supply constraints. Going forward, it will focus on three core areas: high-speed interconnect IP, modular Chiplet products, and open, customizable system platforms.

Quarkchip’s brand communications and product portfolio strategy at IP-SoC China 2026 offers actionable insights for technology brands across brand building, product R&D, and trend identification.

1. Brand marketing: Quarkchip selected Asia Pacific’s leading IP-focused industry conference as its core communications platform. It presented technical breakthroughs and shared industry perspectives at the dedicated AI chip architecture track to build a reputation for deep technical expertise, while also operating an in-person booth showcasing test chips and solution boards. This combined format of professional forum presentations and hands-on product demonstrations effectively targeted specialist audiences, efficiently strengthening the company’s brand recognition as a leader in high-speed interconnect technology.

2. Product R&D and trend alignment: Quarkchip has anchored its product roadmap around the industry shift from computing power competition to interconnect competition for AI chips, targeting core customer pain points including high development costs for multiple IP sets and constrained HBM supply. It has launched domestic IP compatible with multiple interconnect modes, a decoupled IO Die for HBM, and customized 3D storage solutions, with related products already in volume production. These offerings directly address downstream customers’ core priorities of cost reduction and supply chain resilience.

The AI chip technology iteration trends and commercialization milestones detailed in the article highlight clear incremental market opportunities and replicable go-to-market lessons for sellers across the semiconductor supply chain.

1. Incremental market opportunities: The core bottleneck for AI chips has shifted from single-die computing power to system-level interconnect capability, creating clear growth potential for high-speed interconnect IP, modular Chiplet products, and interconnect-aligned storage solutions. In particular, die-to-die (D2D) interconnect has evolved from an optional feature to a foundational architectural requirement for AI chips, driving highly certain market demand for related products.

2. Replicable commercialization lessons: Quarkchip reduces customer adoption costs with a single IP solution that supports both D2D and chip-to-chip (C2C) interconnect, and has launched alternative customized 3D storage solutions to address HBM supply shortages and price volatility. Products targeting core customer priorities of cost reduction and supply chain stability have already entered tape-out and volume production for enterprise SSD controller applications, validating the viability of this go-to-market approach. Sellers can accelerate market entry by developing offerings aligned with these core customer pain points.

The technical specifications and implementation requirements for high-speed interconnect IP and Chiplet products outlined in the article provide clear guidance for production design and new business opportunities for semiconductor manufacturing, packaging, and testing fabs.

1. Production design requirements: Quarkchip’s domestic UCIe interface IP supports standard domestic substrate packaging, covers 2D and 2.5D packaging formats, and supports interconnect distances ranging from 2mm to 25mm. The solution requires zero bit errors over extended operation at 16Gbps and 32Gbps, operates across a wide temperature range of -40°C to 85°C, and delivers power consumption below 1.0pJ/bit. Fabs can refine their packaging, wafer testing, and volume manufacturing capabilities to meet these specifications, matching customer requirements for performance and reliability.

2. Commercial opportunities: As D2D interconnect becomes a core architectural requirement for AI chips, stable order volumes will emerge for UCIe-compatible 2D/2.5D packaging services, volume production of IO Die, and customized 3D memory stacking. Demand for standard substrate packaging compatible with domestic IP is set to grow particularly fast as domestic interconnect solutions enter mass production, allowing fabs to pre-position capacity to meet upcoming customer demand.

The AI chip technology iteration trends and core supply chain customer pain points detailed in the article provide clear roadmap guidance for semiconductor technology service providers.

1. Industry trends and emerging technology segments: The AI chip sector has transitioned from computing power competition to interconnect competition. Interconnect demand is split into scale-up (to improve single-node performance) and scale-out (to enable elastic multi-node expansion), with low latency and low power consumption as core performance metrics. D2D interconnect has become a mandatory architectural foundation for AI chips, creating new service tracks across high-speed interconnect IP services, Chiplet design services, and system interconnect verification services.

2. Customer pain points and solution opportunities: Downstream chip customers currently face pain points including high development costs for multiple sets of interconnect IP, severe HBM supply and pricing constraints, and slow link establishment speeds. Service providers can develop targeted solutions to address these gaps, such as IP services compatible with multiple interconnect standards, 3D storage design services that deliver HBM alternatives, and hardware-level link training optimization, to directly meet customer priorities of cost reduction and supply chain resilience.

The event format and industry technology signals from the latest IP-SoC China conference offer practical operational reference for tech event platforms and semiconductor industry matchmaking platforms across operations, exhibitor recruitment, and content planning.

1. Platform operations and exhibitor recruitment: As Asia Pacific’s annual flagship IP-focused industry conference, IP-SoC China hosts dedicated tracks on high-priority topics including AI chip architecture, invites leading global IP and EDA vendors to share technical insights and collaborate on ecosystem development, and runs a concurrent in-person exhibition area for vendors to demonstrate physical solutions and facilitate supply-demand matchmaking. This model of “cutting-edge topic sharing + physical solution demonstration” effectively attracts technology vendors like Quarkchip and draws large numbers of professional attendees. Platforms can boost industry influence by prioritizing recruitment of high-quality vendors in high-speed interconnect, Chiplet, and AI chip segments.

2. Trend alignment: Platforms need to track the latest industry technology directions in a timely manner. As the core bottleneck for AI chips shifts to system interconnect capability, platforms can tilt agenda setting and matchmaking event planning toward high-speed interconnect IP, modular Chiplet products, and customized storage solutions, ensuring content remains aligned with real industry needs and delivering precise matchmaking resources for all participants.

The assessment of AI chip industry development stages and commercialization progress from domestic vendors outlined in the article provides cutting-edge research samples and industry trend references for semiconductor industry researchers.

1. Emerging industry trends and open questions: The LLM-driven AI chip sector is undergoing a stage shift, with core competition moving from single-die computing power to system-level data delivery capability. Traditional IO solutions are unable to meet interconnect requirements in the Chiplet era, making interconnect technology a core variable shaping the availability and cost efficiency of AI applications. The two core interconnect directions—scale-up for single-node performance improvement and scale-out for elastic multi-node expansion—address distinct demand sets, while D2D interconnect has evolved from an optional technology to a foundational architectural requirement for AI chips. The downstream impacts of this industry shift merit long-term tracking and research.

2. Business models and practical progress: Domestic vendors have developed volume-producible domestic solutions in the high-speed interconnect space. Quarkchip’s UCIe IP supports fully domestic delivery, reduces customer costs with a single IP compatible with multiple interconnect modes, and has launched a decoupled IO Die and customized 3D Memory solutions to address HBM supply constraints, with related products already shipping in volume for enterprise SSD applications. This integrated model of “productized IP + modular Chiplet + open customizable system platforms” provides a valuable practical research sample for the development of China’s domestic Chiplet ecosystem.